Memory Interface Generator 7 Series

Memory Interface Generator 7 Series

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Xilinx 7 series FPGAs do not have hard memory controllers instead, they have hard PHY which exposes DFI interface. DDR Controllers must be used act as a mediator to provide access between user interface AXI and DFI. The MIG creates the controller

Reading

1. https://community.element14.com/technologies/fpga-group/b/blog/posts/exploring-7-series-mig-part—0