Verilog

Verilog

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Registers and Wires

reg can store state, wires can not.

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Assignment

  input   wire    i_S;
  output  reg     o_R;

  always @(posedge i_clk)
  begin
    o_R <= i_S;
  end

<= is a non bloking assignment, and happens on the clock edge. So in the following code the last assignment takes priority.

  always @(posedge i_clk)
  begin
    A <= 5;
    A <= A + 1'b1;
  end

Hardware executed all blocks at once.

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